Webinar: IQ, Image Reject, and Single Sideband Mixers Demystified
May 28, 2020 | 8am PST

Quadrature mixers (IQ, Image Reject, and Single Sideband) are offer powerful capabilities and are critical to modern communication and electronic warfare systems. However, they are also among the most complex RF and Microwave circuits. In this webinar, Marki Microwave will deconstruct these powerful circuits by explaining:
• How ‘quadrature’ signals lead to signal cancellation without filtering
• Common compensation techniques for optimal carrier and sideband suppression
• The best and worst ways to create quadrature signals for any application

IQ Mixer Resources

Q&A

What is the typical image rejection of an IQ mixer?

Marki’s legacy IQ mixers have image rejection of around 20 dB across 4:1 bandwidths or more. New MMIQ series IQ mixers have image rejection as high as 35 dB across the band. Image rejection is more difficult to maintain at higher frequencies and broader bandwidths. At low frequencies with fixed LO the image rejection can be as good as 50-70 dB.

What does the terminology I/Q mean? How are upper and lower sidebands connected?

The I port is for the mixer that is driven with an in-phase LO, and the Q port is for the mixer driven with a quadrature mixer. If you connect an IF hybrid ‘in-phase’ (0° port to I port, 90° port to Q port) then you will select the lower sideband and if you connect it ‘out-of-phase’ (0° port to Q port, 90° port to I port) then you will select the upper sideband.

When you connect a balanced balun to a diode ring to create a mixer, it creates suckouts. How do you mitigate this?

The impedance of a diode ring during mixer operation is highly non-linear and not even a stationary function (it is time varying). Therefore you must codesign the mixer baluns with the diodes while simulating actual mixer operation.

Webinar: Amplifiers for Synthesizer and Local Oscillator Generation: The Unsung Application
May 14, 2020 | 8am PST

Many amplifiers in a typical RF/microwave system are used for single frequency applications: for local oscillator and clock generation. However, amplifiers are typically designed and characterized only for signal applications. In this short (30 minute) webinar, we will discuss:
• Do gain flatness, IP3, and noise figure really matter for LO drivers?
• Phase noise: the impact of amplifier selection
• Save time with more usable amps: positive gain slope, positive only bias, and SWAP optimized drivers

Amplifier Resources

Q&A

Q: Can a Marki Microwave driver amplifier be used as a signal path PA?

The short answer is yes, they can.

The longer answer is that in a lot of RF signal path applications, you may find that the wide bandwidth of the “driver” amplifier offers some versatility for your frequency plan which is really beneficial.  The tradeoff is that wideband amps are usually going to have a step down in power efficiency and/or IP3 when compared to a narrowband alternative.  Really it depends on your particular application and what you need from the amplifier in that spot.  You’ll have to look at the frequency band, the gain, the power output, the noise figure, and the IP3 to see how the overall performance effects your dynamic range when using it.  In short, any amp can be used for any reason, it’s just a question of which performance benchmarks has the designer optimized for, and what are the critical parameters that you need for your system.

Q: Does the DC supply contribute significant phase noise relative to the amplifier it’s supplying?

A: This is a great question!  Yes, the DC power supply can absolutely contribute a large amount of phase noise into the amplifier that we are measuring in additive phase noise measurements.  When we make additive phase noise measurements and show you guys the measurements publicly, we are hiding a lot of the work and trial and error and optimization of the measurement setup that went into the measurement.  We’ve seen that by adding a lot of external bypass capacitance on the power supply pins of the amplifier or even using a voltage regulator on the DC source, we can clean up the measurement quite a bit and get rid of nonphysical humps and spurs that will appear on the data.

Q: How do you remove the oscillator phase noise from the additive phase noise measurement?

Here’s a look at the measurement setup we use:

We have an oscillator that is powered within the phase noise analyzer that is fed through a lot of filtering elements to clean up the signal as much as possible, then it’s amplified further then it’s filtered again.  The oscillator and the driver amplifier add a lot of phase noise into the input signal that is almost always much larger than the phase noise contribution of the DUT we are measuring, especially if it’s an APM low phase noise amplifier!  We are able to suppress this maybe 30 dB or so by splitting out this input tone into 3 paths and then carefully tuning variable phase shifters and attenuators so that the same phase noise in each period is fed in sync to mixers that are in the phase noise analyzer.  This method does have limits, so when measuring very low phase noise amps, it’s very helpful to use an exceptionally clean oscillator to generate that input tone to make it easier to avoid falling into a noise floor in the measurement.  This is something that can difficult to do, as you need to be very careful not just about the phase matching, but also about the power levels that are presented to the DUT and to the phase noise analyzer itself.  It took us a lot of time and effort to be able to start measuring additive phase noise with success and consistency.

Q: Why does phase noise go down when you use parallel amplifiers?

A: The math that goes into this is pretty complicated, but at least to my understanding, this has a lot to do with the amount of current that is flowing into the device, and I believe this is also very related to why the phase noise drops when you drive the amplifier into gain compression – as amplifiers in gain compression will usually pull more DC current.  I’m going to cite Enrico Rubiola on this, as he has a much more complete understanding of this than I do:  See Rubiola’s work here.

At the risk of being slightly inaccurate to try and simplify it, my understanding is as follows:  When it comes to amplifiers, the phase noise comes from the uncertainty in the time it takes for each carrier to make it across the active region of the device – usually because of trap states and the statistical likelihood of a carrier falling into a trap state or escaping from a trap state at any given moment.  This is why FET-based devices have higher phase noise, because FET channels are more or less 2-dimensional channels and surfaces/junctions of materials are riddled with traps, whereas HBTs conduct current through the bulk of the semiconductor.

So if you have more current, you have more carriers crossing the channel at a time.  So I would compare it to if you ran an experiment with 10 coin flips, 100 coin flips and 1000 coin flips and so on.  The larger the sample size becomes, the less overall variation you expect in the total outcome in terms of a percentage.  So more carriers crossing a channel at once causes the probability density function of the randomness in the overall transient uncertainty in each period to collapse towards the expected amount of time per period, which is the period of the carrier frequency.

Q: What do you mean by amplifiers in parallel when talking about phase noise measurements?

We used an RF splitter and then used attenuators to make sure that the DUTs always saw the same amount of input power regardless of the test condition.

Q: Why is there abrupt changes in phase noise in measurements very far away from the carrier in your phase noise measurements/why are there so many spurs in the phase noise data?

A: The short answer here is – phase noise measurements are really hard!  There are a lot of signals involved in the measurement – frequencies within the DC power supply, frequencies in the phase noise analyzer itself, the frequency from the wall power supply, etc.  And we are measuring power levels at extremely low levels (sometimes over 165 dB down from the carrier!).  Extremely minute contributions from all of the circuitry involved in the measurement can result in some pretty dramatic spurs at that level, and it’s quite difficult to truly clean up the data entirely.  We also end up seeing some pretty bizarre non-physical behavior when you get far away from the carrier or very close to the carrier.  This is some of the reason why phase noise is usually quantified at 10 kHz offset from the carrier – you’ll notice that this is the region where the measurement is the most clear and clean.  When you see phase noise data with no spurs, the reason is usually because the spurs were manually removed from the data.  We’ve observed this effect on multiple types of measurement systems.

Q: Why does positive gain/Psat slope offset losses from interconnects?

A: Since the interconnect losses are higher at higher frequencies, a lot of system designers will put some equalizers into their chain to add a little more loss at the low end than at the high end to level out the overall spectrum.  In the case of a positive gain slope (or a positive Psat slope if in gain compression), you are basically building an equalizer into your amplifier curve, so it accomplishes the same thing.

Q: Is it necessary to use a linear regulator after the charge pump in your UC5 board?

A: We don’t but this was something we considered when we were designing it.  The inverting charge pump does use an internal oscillator to generate the negative voltage, however, the magnitude of this oscillator tone that comes out is proportional to the current that you are drawing out from it.  Since this is a FET based device with nominally zero gate current, the tone contribution was miniscule.  We measured this and put a section for it on our website, but even without a linear regulator on this negative voltage, the power of this spur was suppressed by about 100 dB from the carrier, so it’s pretty hard to imagine that actually impacting anyone’s system performance.

Q: Can even harmonic distortion presented to the LO of a mixer cause a DC offset that would require DC blocking?

A: Usually the LO port of a mixer is either an open or a short to ground, so most of the time it won’t matter much in this regard, but even harmonic distortion in the LO can manifest itself as a duty cycle distortion in the mixer and it degrades the multi-tone suppression.

Webinar: A Brief Guide to Mixer Spurs
April 30, 2020 | 8am PST

Spurious products can quickly overcrowd your output spectrum and destroy the dynamic range of your system if you aren’t careful. The threat of these spurs can be minimized if a designer can predict their exact frequency and power early in the design phase. In this short (45 minute) webinar, we will discuss:
• Where single tone intermodulation products come from within a mixer
• How to model a mixer to get close approximations of spurious levels
• How to get the most accurate prediction possible without sitting in front of a VNA

Mixer Resources

Q&A

Webinar: Microwave Amplifier Biasing Made Easy
April 16, 2020 | 10am PST

Optimal amplifier biasing can make a direct impact on the performance of your system. However, choosing the correct bias levels for your application can be challenging, and there are a number of factors that are often overlooked. In this short (25 minutes) webinar, we will provide insight into:
• Important distinctions between amplifier topologies
• Biasing considerations to improve noise filtering, reliability, and electrical performance
• Heat: why it’s a stronger factor than you might think

Amplifier Resources

Q&A

How much sooner than the positive bias does the negative need to be applied?

For depletion mode FETs and HEMTs, we mentioned that the negative gate bias should be applied before the positive drain supply voltage. We believe that it would be roughly on the order of nS-µS that the gate would need to be applied prior to the drain voltage. Through simulation, we’ve discovered that the gate seems to turn on much faster than the drain voltage.  Because of this, I believe that it may be more dangerous turning voltages OFF together than turning them ON together. In our lab experience, we have not noticed any damage occurring when applying the gate and drain voltages at the same time, but this may result in reduced long-term lifetime.  In many circuits, you will see a momentary ringing effect in the actual applied voltage for extremely rapid simultaneous turn-on or turn-off, but in most application circuits there is enough capacitance in the power supply and/or the bias lines to prevent any serious danger from this.

If you have bias oscillations in your system or test, how do you track them down? How do you fix them?

Oscillations can be difficult to discover when using just a network analyzer to test your amplifier. The best way to track them down is to use a spectrum analyzer. First, apply the DC supply and bias voltages and monitor the output of the amplifier for any unknown spurs while sweeping the spectrum analyzer. If you see any spurs, then you know you have an oscillation at that frequency. Next, you can input a single tone frequency using a signal generator and sweep that frequency to check for any unwanted spurs that arise. It is also important to recognize that oscillations could occur at any bias point or frequency combination, so you have to move around the frequency while monitoring the output in kHz-MHz ranges around the signal frequency. It’s also helpful to decrease the IF bandwidth on the spectrum analyzer and zoom in around your tone frequency to get higher resolution. Oscillations often occur at low frequencies and then mix up with the fundamental frequency, creating a periodic arrangement of spurs that resemble a picket fence on your spectrum analyzer monitor.

To fix these oscillations it usually requires a lot of trial and error. It typically requires adjusting the bias circuitry with different bypass arrangements. Multistage amplifiers can have unwanted feedback paths that create a in-phase positive gain loop that will cause output power suck outs, other spur mixing tones, and increased power consumption. This can often be a subtle problem that should be tested if you are having issues in your system.  If you have any issues of this kind with any Marki amplifiers, we encourage you to reach out to [email protected] for assistance.  We have spent a lot of time trying to protect against these issues, and will happily share what we have learned about our parts.

Does it make a big difference if I bias for a fixed current, like most pHEMT amplfiiers say I should, or just use a fixed bias?

It typically does not make a big difference. However, if you are trying bias for very repeatable performance, then you should bias for a fixed current. We have noticed that for pHEMT amplifiers we can see as much as 5-10% variation in the current pull with a particular gate bias, so it’s best to design for a fixed current if you are after repeatability. However, this can be a pain for most of our customers to design around a fixed current pull. Therefore, on our datasheets we demonstrate performance for fixed gate and drain biases.

Will you provide specific harmonic data for your amplifiers on request?

Yes! We are happy to take specific measurements for our potential customers.

how do the various packages (bare die, SMT, and module) affect performance and how do you mitigate that in your design?

Bare die is the cleanest version of the amplifier because you don’t have to account for the extra parasitics you get from the packages. Surface mounts have the most extra parasitics from the vias which add some capacitance and inductance. The wire bonds from the vias that are connected to the board add additional impedances, which is why the surface mount packages have the most variation of the three. Modules typically show similar performance to the bare die, except they might have a minor increase in insertion loss from the extra transmission lines in the package.

What is the max bias current supply for Marki sequencer circuit? Does it have turn off sequence?

The current necessary to operate the charge inverter causes an approximate 30mA increase in the supply current draw. The amplifier itself can potentially run up to 400mA of current pull when driven with high input power, and that is what we have listed as our safe operating maximum on our datasheet for the AMM-6702UC5. If you turn on the supply voltage on the order of µS, then the current to the amp will not turn on before the gate bias is applied. However, if you turn on the supply voltage to the sequencer very quickly, on the order of nS, then you do notice some overlap between the gate and drain bias. The design is safe to the turn off sequence and we have not noticed any problems with how fast you turn off the supply voltage.

For distributed amps, we’ve recently seen some trends in bias that differ from typical Class A amplifiers. In particular, we’ve seen second order product performance correlate more strongly to drain current, and third order product performance correlate more strongly to drain voltage. Do you have any insight on what causes these trends and whether they may be fundamental properties of these amps or perhaps specific to individual designs?

The typical slope of a class A amplifier load-line is for a particular impedance presented to the transistor at a particular frequency, and distributed amplifiers are typically designed for broadband applications. Therefore, distributed amps are only truly class A at one frequency, and as you go across the band the slope of the load line will move around quite a bit, which will impact the linearity and the appearance of harmonic products.  If you change the bias voltage, you’ll change the frequency at which you have your best power match, and you’ll overall increase the linearity of the amplifier a bit by creating more voltage headroom.

Regarding the third order products, typically for a stack/cascode of amplifiers you will see the third order products increase as the amplifier is driven with higher input powers, regardless if it is a distributed amplifier or not. This means that if you have more available output power before you enter saturation, then the third harmonic generation will not be as present at lower input powers. As you increase the drain current, you will see lower power third order products and correspondingly higher third order intercept.

Do any of the HBT amps need sequencing, or is it just the pHEMT amplifiers?

Just the depletion pHEMT amplifiers require sequencing. The HBT’s base voltage is controlled by a current mirror that does not allow much current to flow through the collector of the RF transistor unless there is sufficient positive bias voltage applied. Only the AMM series of amplifiers require sequencing in their turn on procedure in Marki’s catalog, and that does not include the new UC5 package which is internally sequenced.

Webinar: Baluns, Balance & Differential Signals
April 2, 2020 | 10am PST

Differential signals and circuits have a magical property: the ability to cancel undesired signals without filtering. In this short (25 minute) webinar we will present:
• The Three Mistakes Everyone Makes When Using Differential Circuits
• How Balanced Circuits Can Give You Better Noise Suppression, Spur Cancellation, and More Power
• The Best Balun to use for Every Situation

Balun Resources

Q&A

What is the difference between the BAL and BALH series?

The BAL series has resistive matching on the output that improves the input return loss the BALH series does not. Read more here: BAL vs. BALH and Microwave Black Magic

Which mixed mode scattering parameters correspond to common mode rejection ratio and other factors?

It is important to define what you want to get out of the common mode rejection ratio (CMRR). Do you want the ratio of insertion loss to common mode signal generation? Or do you want to know what kind of isolation to expect from a mixer? In general the common mode rejection can be expressed as the insertion loss off the common mode to the single ended mode, or S12sc. See more here: Mixed Mode Scattering Parameters: What Are They and How Do I Use Them?

What is the difference between a voltage and current balun? Which type does Marki make?

Read about that here: Current vs. Voltage Baluns

What is the difference between a common mode choke and a balun?

I have to admit I wasn’t familiar with the term, but a common mode choke is a differential in – differential out (a ‘balbal’?) device that has a high insertion loss for common mode signals. Coilcraft has a good writeup on them here, and the operate to surprisingly high frequencies. If you wanted to make such a device to microwave or mm-wave frequencies you could put two baluns back to back, but it would be pretty lossy.

Can you give me any tips on designing and building wirewound baluns? What are the tradeoffs in different topologies (Marchand, Ruthroff, Guanella, etc)?

As a balun company I’d rather not give you any tips on building high frequency type baluns. If you are interested in lower frequency wirewound baluns I recommend Jerry Sevick’s Understanding, Building, and Using Baluns and Ununs. This is a great resource, although it looks like it has gotten pricey since it might be out of print. There are many other article’s in the Ham literature for hobbyists.

Do you have any recommendations for matching from a balun into an ADC?

Yes, contact Rob Reeder at Texas Instruments or Umesh Jayamohan at Analog Devices.

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