by Kyle Chang
In my previous tech note exploring TDR as a method for optimizing surface mount footprints, we determined the root cause of the evaluation circuit’s performance degradation and added an inductive taper to the launch to improve impedance matching. By optimizing the PCB launch into the package, insertion loss and return loss performance significantly improved (Figure 1). In this tech note, we will break down surface mount packaging parasitic sources and present solutions to combat these undesirable parasitics.
Figure 1. S-Parameters for Original (Left) and Updated (Right) MMIC BPF Evaluation Circuit.
Packaging MMIC Filters
Marki’s GaAs MMIC filters are packaged in 5×5 mm plastic QFNs. Our go-to QFN package style is the air cavity QFN (Figure 2) – this is preferred over the overmolded plastic QFNs since air cavity packages isolate the circuit from additional losses and dielectric loading due to the overmold compound. Plastic overmolded packages also run the risk of warping or breaking wire bonds if the pressure from injecting the plastic is substantial enough.
Figure 2. Cross-section of Air Cavity QFN Package with GaAs Die.
In short, air cavity QFNNFs are assembled as follows: first, the GaAs chip is glued down to the ground pad with conductive epoxy to the ground pad, then the wire bonds are attached from chip to leads, and finally the lid is epoxied on to the package. Sounds pretty simple, right? Unfortunately, packaging chips into SMT devices creates additional interfaces and interconnects that which have parasitic capacitances and inductances – these become increasingly noticeable with higher operating frequencies.
Packaging Parasitics
Parasitic capacitances, inductances, and resistances are found on every interconnect and transition within a package (Figure 3), however a basic model can be derived from several major parasitic contributors:
Figure 3. Parasitic Model of RF Path from PCB to Chip.
The RF path network from the PCB trace to the chip forms a low-pass network – we start with package capacitance CPK, which is associated with the capacitance seen between the lead and ground paddle and the capacitance from the lead to ground plane through the PCB trace. Additionally, the grounded leads in parallel with the RF path lead also contribute to the parasitic capacitance. From the package lead to the chip, the wire bond contributes inductance LWB and a negligible resistance RWB to the RF path. On the chip side, there is parasitic capacitance CBP from the bond pad to the ground pads.
These parasitics are inherent to the package and chip, however some of these effects can be minimized. For inductance in the RF path, increasing the number of parallel wire bonds from chip to lead will decrease inductance, however the number of additional bonds is limited to bonding pad and lead pad space constraints. Additionally, decreasing the length and loop height of the wire bond decreases resistance and inductance, resulting in decreased insertion loss. Bond pad capacitance CBP can be compensated for by designing inductive elements within the bond pad. Thankfully, Marki’s MMIC filters have you covered; we’ve taken care of parasitics from within the package… and outside, too!
Optimizing PCB Launches
Typically, bond pads are well-matched to 50Ω on chip while PCB traces leading into the QFN are also designed for a well-matched 50Ω transition. However, those pesky parasitics mentioned earlier cause impedance mismatches and cannot be fully eliminated – instead, designers must compensate for this mismatch somewhere along the design. For those implementing our QFN packaged MMIC filters, compensation will occur on the PCB launch into the package. As we explored in a previous tech note, we minimized wire bond inductance LWB within the package, however there is still package capacitance CPK as a result of trace to ground and lead to ground pad capacitances. The dimensions of the PCB pad and package leads are restricted due the design of the package, limiting adjustments to CPK. Instead, our suggestion is to introduce an inductive taper to counter the parasitic capacitance:
Figure 4. Suggested Footprint for MFBC-00004PSM.
After running numerous experiments, simulations, and design iterations, Marki’s design team has optimized a PCB launch for each of our filters. For frequencies at 15GHz and above, parasitics become prevalent and degrade insertion loss enough to warrant adding inductive tapers to our PCB launch. For devices such as MFBC-00004PSM with a -1dBc passband from 18.6-25.1GHz, the suggested inductive taper dimensions are shown in Figure 3 and on our datasheets. For MFBC’s with higher passband frequencies, the inductive neck has been adjusted similarly to reduce degradation caused by package capacitance CPK.
We provide suggested landing pattern designs as DXF files for our MFBA and MFBC MMIC filters optimized for 8 mil Rogers 4003, as shown on our datasheets. These designs are implemented on all our evaluation boards (such as the eval board designed for MFBC-00004PSM), which are perfect for building into system-level prototype designs or running experiments in the lab.
Figure 5. Outline Drawing for EVB-MFBC-00004P.
Conclusion
Packaging chips in to SMT devices introduces additional sources of parasitics that are unavoidable; at high operating frequencies, every element from PCB trace to the chip has intrinsic parasitic capacitances and inductances causing deviations from the 50Ω we’ve worked so hard to create on the PCB and chip. However, Marki’s MMIC filters come with optimized landing patterns to compensate for those nasty parasitics, so don’t let debugging parasitics become a headache for you.
For any questions about landing pattern design for Marki’s packaged MMIC filters, please reach out to [email protected] – we’re happy to help you shatter performance barriers on your next design!
