By Kyle Chang
As microwave designers push surface mount systems to higher frequencies of operation, the detailed layout of circuitry on a surface mount board becomes more important. This is particularly true for components that are designed to be low insertion loss and high return loss, such as Bias Tees, Couplers, Equalizers, Filters, Power Dividers, Limiters, and Switches. These components are codesigned with a particular PCB footprint for optimal high frequency match, and this footprint is included in the datasheet. However, this footprint is based on a particular board stackup (circuit material and thickness), which a designer may not be using. A surface mount component has attachment pads that are typically more capacitive than a 50-ohm match would require, which means that some extra inductance is required to improve the match. In this article we will demonstrate a technique to experimentally determine the optimum inductive match for a surface mount component.
Time-domain reflectometry (TDR) is a useful tool traditionally used for applications such as determining cable length, fault locations, impedance changes, and various electro-mechanical features of transmission line cables that are either buried, very long, or dangerous to reach. At much higher frequencies, we can use this tool on much physically shorter transmission lines where we don’t have the same inaccessibility issues – instead the issue lies in the inability to see microscopic faults and invisible parasitics. Without a means to determine fault locations with the naked eye, TDR proves a powerful tool in visualizing impedance types and variations on a microstrip.
TDR instruments operate similar to a radar system by sending a step pulse down a transmission line to the device under test (DUT) and monitoring for reflections caused by impedance mismatches along the way. Using time measurements and a known propagation velocity, the TDR can determine the distance to the reflection. To determine type of discontinuity, we calculate the reflection coefficient magnitude ρ:
where ZL is the load (or discontinuity) impedance and Z0 is the characteristic impedance. A reflection coefficient of +1 indicates an open circuit and a -1 indicates a short circuit. Ideally, the reflection coefficient is zero indicating a matched line. On a TDR plot, a unit of magnitude (typically voltage, impedance, or reflection coefficient) is plotted as a function of time. Figure 1 shows an example TDR plot for an open circuit where the reflection coefficient is plotted over time. The TDR looks at the response after trasversing the transmission line, so after propagation delay TP, the step response reaches the load at the end of the transmission line, and after 2TP, the reflected response from the load is seen at the TDR. For an open circuit, the magnitude response shows either the reflection coefficient is +1, the impedance shoots towards infinity, or the voltage value doubling the transmitted pulse value depending on the setting selected. The time axis can be converted to a distance measurement when provided the propagation factor of the PCB material.
Figure 1: Example TDR Plot for Open Circuit.
Figure 2 shows step responses to common terminations – in particular, note that the capacitive loads have a slight negative dip before tending towards an open circuit response and the inductive loads have a positive bend before tending towards a short circuit response (this should be familiar from transmission line analysis). On the TDR plot, we see parasitic inductance or capacitance as positive or negative dips in impedance respectively as a function of distance.
Figure 2: Step Response to Common TL Load Terminations.
Experimental Setup and Results
Recently, VNA measurements indicated poor return loss on one of our evaluation boards used to test 5mm QFN packages. Using TDR, we can determine what the issue is and where we can find it. Our VNA, like many modern VNAs, has an option to emulate a TDR test system by performing a Fourier transform on the frequency response of the DUT.
We configured the VNA for a low-pass step response and set the velocity factor to ~0.57 for the Rogers 4003 board material. By calibrating the VNA to our board’s properties, we have accurate distance measurements using the VNA markers – these translate directly to caliper measurements on the eval board. In the configuration shown on Figure 3, the end-launch pin to CPW transition is at ~7 mm and the CPW to QFN pad transition is at ~18 mm from the edge of the connector – these are confirmed by TDR measurements as seen in later figures.
Figure 3: Example Eval Board.
Based on the previous analysis, any positive peaks indicate an inductive response while negative peaks indicate a capacitive discontinuity. Figure 4 shows the TDR response of the original eval board.
Figure 4: TDR Response on Faulty Eval Board.
Near the TDR launch on the left side, we see some ripples in impedance through the adapters leading into the eval board connector. This impedance deviation is insignificant relative to the remainder of the TDR plot, so the adapters are not likely to be the cause of our poor return loss.
Right at the end-launch pin, there is a large capacitive dip caused by the transition between end-launch connector and PCB trace. This transition does not use a solder joint as the connector relies on an interference fit, however there is still a large capacitive dip due to the discontinuity. This transition has already been optimized by using a tapered transmission line end to slightly increase inductance – this compensates for the capacitive transition, however it also introduces some “ringing”. Without the tapered trace compensation, there would be a significant impedance dip well beyond the current level.
Marker 2 at 43mm is consistent with the QFN package edge when measured from the starting edge of the adapter. The capacitive dip after marker 2 on the plot is caused by the capacitance in the transition from the CPW to the QFN pad. This excessive mismatch is likely the root of our poor return loss. The large solder joint area and internal package capacitance contribute largely to this parasitic capacitance. Since the pad size and internal package structure is constrained by the QFN package design rules, we need compensate for the capacitance by increasing inductance on the CPW leading into the QFN. This is accomplished by increasing tapering on the CPW ends to decrease the trace area, and hence capacitance, under the QFN pad.
The positive spike in the transition towards open circuit is caused by the inductance from the wire bonds. To decrease the amplitude of the response, we can decrease the inductance by increasing the number of parallel wire bonds from pad to chip. As we travel further down the line, the TDR response shoots off to infinity indicating an open circuit. This is expected as per design of the surface mount bandpass filter (BPF).
Changing out the BPF for another one with less wire bond inductance, the TDR plot is shown for the same eval board (note the distance is now recalibrated to the edge of the connector to account for the adapters on the cable – the 7 mm marker lines up with the pin launch in Figure 3):
Figure 5: TDR Response on Compensated Eval Board.
With the increased number of wire bonds within the QFN, the inductive spike is eliminated, and we see a smooth transition from the pad-to-pad capacitance to the open circuit response within the BPF QFN chip.
After applying the increased tapering to the DUT end of the eval board trace, we took another TDR response on the VNA to confirm these fixes improved the impedance matching.
Figure 6: TDR Response on Compensated Eval Board vs Original Eval Board.
We can see that the higher trace inductance compensates for the capacitance caused by the PCB pad to QFN pin transition. Compared to the original eval board, the capacitive dip is eliminated, and the impedance mismatch occurs over a shorter length relative to the original PCB. The result is smoother response on the TDR plot indicating a better impedance match overall. The figures below show the before and after s-parameters for our faulty and updated eval boards.
Figure 7: S-Parameters for Original (Left) and Updated (Right) Eval Boards.
On the left VNA capture, the return loss on the original eval board was lower than expected, and the insertion loss shows up to 1dB ripples in the passband. With TDR, we determined that the eval board had excessive parasitic capacitance and updated the boards to compensate for this capacitance. Shown on the right VNA capture is the updated eval board – we have better return loss averaging 10dB improvement across the band and an insertion loss response with zero ripple in the passband.
Using the VNA’s TDR function proved useful in troubleshooting signal integrity issues. With a few clicks on the VNA, we can quickly debug how and where impedance fluctuations can cause poor performance on our eval boards.
In this note we have detailed a procedure using TDR to improve the match of a high frequency Marki surface mount component. Marki is committed to the success of our customers realizing high performance surface mount systems. For assistance with any aspects of your design, related to our components or not, please reach out to us at [email protected].